1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, an SRAM and a method of fabricating the same.
2. Description of the Related Art
FIG. 32 is a plan view showing a memory cell of a conventional SRAM disclosed in Japanese Patent Application Laid-Open No. 45796/1997. Active regions 112a, 112b, 112c, and 112d are formed on the main surface of a silicon substrate 111. Source and drain regions in the active regions 112a and 112b are n-type and source and drain regions in the active regions 112c and 112d are p-type. These active regions 112a, 112b, 112c, and 112d are isolated from each other by a field oxide region 113.
A first conductive layer 116a extends from an area on the active region 112c to an area on the active region 112a. The first conductive layer 116a is a gate electrode for a load transistor Q.sub.6 and a driver transistor Q.sub.4.
A second conductive layer 116b branches from the first conductive layer 116a on the field oxide region 113 and extends toward an area on the active region 112b.
A third conductive layer 116c passes across the active region 112b and the active region 112d, bends on the field oxide region 113, and extends toward an area on the active region 112c. The third conductive layer 116c is a gate electrode for a load transistor Q.sub.5 and a driver transistor Q.sub.3. Note that access transistors Q.sub.1 and Q.sub.2 are not shown in this figure.
FIG. 33 is a cross section of the memory cell of the SRAM along the A--A line. A p-type well 110a and an n-type well 110b are formed on the silicon substrate 111. The active region 112a is formed on the p-type well 110a, and the active region 112c is formed on the n-type well 110b. The active region 112a is isolated from the active region 112c by the field oxide region 113.
The second conductive layer 116b is formed on the field oxide region 113. Side wall insulating films 117 are formed on the sides of the second conductive layer 116b.
The conventional SRAM shown in FIG. 32 has two problems. First problem will be described below.
The SRAM shown in FIG. 32 is formed by laminating a conductive layer and an insulating layer on the main surface of the silicon substrate 111. A mask alignment is indispensable in this lamination step. A mask alignment error may occur in such a mask alignment. FIG. 34 is a plan view of a memory cell showing a mask alignment error caused by a mask shifted in the direction of the Y axis at the time of forming the first conductive layer 116a, the second conductive layer 116b, and the third conductive layer 116c. FIG. 35 is a cross section of the memory cell of the SRAM shown in FIG. 34 along the A--A line.
In FIGS. 34 and 35, part of the second conductive layer 116b and the side wall insulating film 117 overlap the region designed to be the active region 112a. Because of this, the gate width of the gate electrode of the driver transistor Q.sub.4 is W in the plan but actually is w, which is smaller than W. This causes an imbalance in the .beta. ratio (capacity ratio of driver transistor to transfer transistor), causing the characteristics of the SRAM to deteriorate.
It is therefore necessary to take the mask alignment error into account when designing the layout of the SRAM. As shown in FIG. 33, the width of the field oxide region 113 must be wide enough to allow the second conductive layer 116b and the side wall insulating film 117 to be located on the field oxide region 113, even if the mask alignment error occurs. However, this goes against the need for a reduced memory cell size.
Second problem is as follows. FIG. 36 shows an end section of the active region 112c shown in FIG. 32. In the plan, the active region 112c is designed to be within a solid line 119, but actually, the active region 112c is formed within a broken line 120 due to a bird's beak 118. Since the active region is narrow in the end section of the active region 112c and oxidized from three directions in a LOCOS process, the effective active region is small as shown in FIG. 36. The active region 112c is in contact with an upper wiring layer. If the area of the active region 112c is small, the margin is reduced when the active region 112c is connected to the wiring in the upper layer.